A programmable logic device (PLD) is a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, multipliers, processors).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed in a configuration process by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM (programmable read-only memory)) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the complex programmable logic device (CPLD). A CPLD typically includes two or more “function blocks” or “macrocells” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in programmable logic arrays (PLAs) and programmable array logic (PAL) devices.
For all of these programmable logic devices, the functionality of the device is controlled by data bits, or configuration data, provided to the device for that purpose. The data bits can be stored in the PLD in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in nonvolatile memory (e.g., flash memory, as in some CPLDs), or in any other type of memory cell. In some cases, particularly where the PLD stores configuration data in volatile memory, the data is provided to the PLD by an external nonvolatile device. For example, an FPGA can be configured by an external nonvolatile memory such as a PROM. In this way, configuration data can be preserved when power is not being supplied to the system. As another example, configuration data can be provided to a PLD by another external configuration device, such as a processor or microcontroller.
PLDs that store configuration data in volatile memory receive that data during the configuration process. Typically, at power-up (or at any other time a PLD is configured), the external configuration device, such as an external PROM or processor, transfers the configuration data to the volatile memory of the PLD through a pre-defined interface. For example, the configuration processes for the Virtex™-II series of FPGAs manufactured by Xilinx®, Inc. of San Jose, Calif. (“Xilinx”), is set forth in Chapter 3 of the “Virtex-II Platform FPGA Handbook,” UG002 (v1.0) 6 Dec. 2000 (the “Virtex-II Handbook”), which is incorporated herein by reference.
As is common in all electronic designs, a designer often faces the challenge of debugging a non-functional design. When designing for a PLD, there are many possible reasons that a PLD may fail to function as intended by the designer. One problem unique to PLDs that can cause failure is a problem arising during the configuration process. For example, the configuration data being supplied to the PLD from the external configuration device may have been corrupted in transit. As another example, the external configuration device may be providing the wrong or otherwise flawed bitstream. Many other problems can occur during the configuration process. Often these problems can be difficult, or even impossible, for most users to debug.
Therefore, there is a need for methods and tools for debugging the configuration process in PLDs.